1. Field of the Invention
The present invention relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof, and in particular, to a fractional-N frequency synthesizer capable of improving in-band noise while out-band pushing quantization noise occurring in a sigma-delta modulator by substantially increasing a clock frequency M times using M phase/frequency detectors and M charge pumps instead of increasing a clock frequency of the sigma-delta modulator M times and a method thereof.
2. Description of the Related Art
A frequency synthesizer is essentially used in a wireless communication system to obtain a channel frequency required for a receiver and a transmitter as well as in devices using frequency. The frequency synthesizer generates a desired channel frequency in a manner that a phase of a frequency signal of a predetermined reference frequency ‘fref’ is compared with a phase of a frequency signals generated by dividing an oscillation frequency of a voltage controlled oscillator by a required division ratio by using a phase locked loop (PLL).
As the dividing schemes of the phase locked loop, there are an integer-N scheme and a fractional-N scheme. The fractional-N scheme is a scheme that can divide the oscillation frequency of a voltage controlled oscillator by a division ratio having a fractional value.
In order to make a lock time and a phase noise good, the fractional-N frequency synthesizer should use a wide closed loop bandwidth. However, in order to generate the desired frequency, a decimal value is needed, which is obtained by using a sigma-delta modulator. The sigma-delta modulator causes a further noise called quantization noise. The entire phase noise performance is degraded due to the quantization noise. Therefore, in order to reduce the quantization noise, the related art used a method of reducing the closed loop bandwidth or increasing the clock frequency of the delta-sigma modulator.
FIG. 1 is a block diagram showing a fractional-N frequency synthesizer according to the related art. The fractional-N frequency synthesizer according to the related art includes a reference oscillator 10, a sigma-delta modulator 20, a divider 30, a phase/frequency detector 40, a charge pump 50, a loop filter 60, and a voltage controlled oscillator 70.
First, in the fractional-N frequency synthesizer according to FIG. 1, when the closed loop bandwidth is reduced, the quantization noise of the sigma-delta synthesizer is pushed to out-band. This characteristic can reduce the quantization noise outside the loop bandwidth due to the low-pass characteristic of the phase locked loop (PLL). However, when the bandwidth is wide, the quantization noise is added to the output of the frequency synthesizer to degrade the entire noise characteristics, such that there is a problem in that the quantization noise, which is the out-band noise source, becomes a dominant noise source of the entire fractional-N frequency synthesizer.
Meanwhile, FIG. 2 is a block diagram showing the fractional-N frequency synthesizer according to the related art that increases the clock frequency in order to reduce the quantization noise of the fractional-N frequency synthesizer according to the related art.
The fractional-N frequency synthesizer according to FIG. 2 further includes an incremental device 80, which increases a reference frequency signal twice, in addition to the frequency synthesizer according to FIG. 1. In order to reduce the quantization noise, the method of increasing the clock frequency of the sigma-delta modulator increases the reference frequency signal twice and increases the clock of the sigma-delta modulator twice, such that the quantization noise is shifted to the out-band and the noise is reduced due to the low-pass characteristic of the PLL.
However, when the reference frequency signal, which is the input signal of the phase/frequency detector, is increased M times, the in-band phase noise of the PLL is increased by 10 log(M). In addition, when the reference frequency signal is increased M times, the value of the divider 30 is reduced M times, such that the in-band phase noise is reduced by 20 log(M). In other words, when the reference frequency signal is increased M times, it is limited to 10 log(M). In addition, there is a problem in that the noise in a circuit that increases the reference frequency signal twice increases the in-band noise.